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International Workshop on Advances in VLSI Circuit Design and CAD Tools (AVCDCT13)

August 22-25, 2013, Mysore, India

VLSI circuit design inherently consists of power, speed and area constraints. With changing market needs, emphasis is shifting towards power aware and high performance circuit designs. With ever increasing transistor integration, new advances are seen in the concerned design strategies and related tools enabling implementation of cost effective, low power high performance VLSI circuits. 

International Workshop on Advances in VLSI Circuit Design and ECAD Tools (AVCDCT13) aims to bring together the active researchers, academia, scholars and professionals in VLSI domain to present the latest developments, efforts and their achievements. The motivation is to identify and collate the new techniques, algorithms and implementation for improving the VLSI circuit performance and VLSI CAD Tool sets. 

AVCDCT -2013 is affiliated with International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013), Mysore, India. The event will be held on August 22-25, 2013 in Mysore, India. Mysore, known as the City of Palaces, is one of the most preferred tourist destinations in South India.

Call for Papers

AVCDCT-2013 invites technical papers describing original, previously unpublished results in all areas VLSI improving the circuit parameters and different CAD tool capabilities.Authors should submit their papers online using EDAS. Unregistered authors should first create an account on EDAS to log on. Further guidelines for submission are posted at:

Topics of interest include but not limited to:

  • VLSI circuit design techniques
  • VLSI algorithms
  • VLSI low power design
  • High performance circuits
  • VLSI design 
  • Emerging techniques 
  • Testing methodologies
  • Different VLSI applications
  • SOC and concerned routing topologies/networks
  • CAD tool capabilities
  • Identification of new CAD tool feature list

KiSE'13 EDAS Submission

All papers that conform to submission guidelines will be peer reviewed and evaluated based on originality, technical and/or research content/depth, correctness, relevance to conference, contributions, and readability. The manuscripts should be submitted in PDF format. Acceptance of papers will be communicated to authors by email. At least one full paying author of each accepted paper must register for the Conference before the indicated deadline. Accepted papers will be published in the ICACCI 2013 Proceedings which will be available through IEEE Xplore® after the conference.

Key Dates

 Paper Submission Ends  25 May 2013
 Acceptance Notification  15 June 2013
 Final Paper Deadline  11 July 2013 
 Author Registration Closes  14 July 2013
 Conference  22 – 25 August 2013






Technical Programme Committee

Organizing Chair

ManeeshaGupta, NetajiSubhas Institute of Technology, India

Program Chairs

Manoj Sharma, BVCOE, AFF-G.G.S.I.P.Univ. Delhi, India

Kunwar Singh, Delhi Technical University, India

AnkurSangal, Coreel Tech, India

TPC Members

AlpanaAgarwal, Thapar University, India

AmitPurwar, NVIDIA, India

Arti Noor, CDAC Noida, India

Asral Bahari Jambek, Universiti Malaysia Perlis, Malaysia

Ayman El-Saleh, University Multimedia (MMU), Malaysia

Bakhtiar Affendi Rosdi, Universiti Sains Malaysia, Malaysia

ChauhanHari, Northeastern University, USA

Deva Nand, DTU, India

Elias Rachid, USJ, Lebanon

Hamzah Ahmad, University Malaysia Pahang, Malaysia

Hari Chauhan, Northeastern University, USA

Madan Mohan Tripathi, Delhi Technological University, India

Manoj Duhan, DeenbandhuChhotu Ram University of Science & Technology, India

M M Tripathi, DTU, India

Norlaili Mohd. Noh, Universiti Sains Malaysia, Malaysia

Razaidi Hussin, Universiti Malaysia Perlis, Malaysia

Rizalafande Che Ismail, Universiti Malaysia Perlis, Malaysia

S C Tiwari, Cadence, India

Shankar Duraikannan, Asia Pacific University of Technology and Innovation, Malaysia

Varun Kumar, Mentor Graphics, India

Vigyan Jain, STMicroelectronics, India

Widad Ismail, Engineering Campus, Universiti Sains Malaysia, Malaysia

Xuan-Tu Tran, Vietnam National University, Hanoi, Vietnam

Accepted Papers

1569781199 Design and Analysis of Mux Using Adiabatic Techniques ECRL and PFAL
1569777515 Reconfigurable Digital Sequential System on Chip Design with Its Analysis of Various Parameters & Power Reduction Using Dynamic Partial Reconfiguration
1569786067 Design and Implementation of a High Performance Computing System Using Distributed Compilation
1569773137 An Efficient Delay Estimation Model for High Speed VLSI Interconnects
1569782653 Computer Aided Partitioning for Design of Parallel Testable VLSI Systems

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