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Second International Workshop on Advances in VLSI Circuit Design and CAD Tools (AVCDCT-2014)

VLSI circuit design inherently consists of power, speed and area constraints. With changing market needs, emphasis is shifting towards power aware and high performance circuit designs. With ever increasing transistor integration, new advances are seen in the concerned design strategies and related tools enabling implementation of cost effective, low power high performance VLSI circuits. 

Second International Workshop on Advances in VLSI Circuit Design and ECAD Tools (AVCDCT14) aims to bring together the active researchers, academia, scholars and professionals in VLSI domain to present the latest developments, efforts and their achievements. The motivation is to identify and collate the new techniques, algorithms and implementation for improving the VLSI circuit performance and VLSI CAD Tool sets. 


AVCDCT-2014 invites technical papers describing original, previously unpublished results in all areas VLSI improving the circuit parameters and different CAD tool capabilities.Authors should submit their papers online using EDAS. Unregistered authors should first create an account on EDAS to log on. Further guidelines for submission are posted at:

Topics of interest include but not limited to:

  • VLSI circuit design techniques
  • VLSI algorithms
  • VLSI low power design
  • High performance circuits
  • VLSI design 
  • Emerging techniques 
  • Testing methodologies
  • Different VLSI applications
  • SOC and concerned routing topologies/networks
  • CAD tool capabilities
  • Identification of new CAD tool feature list


All papers that conform to submission guidelines will be peer reviewed and evaluated based on originality, technical and/or research content/depth, correctness, relevance to conference, contributions, and readability. The manuscripts should be submitted in PDF format. Acceptance of papers will be communicated to authors by email. At least one full paying author of each accepted paper must register for the Conference before the indicated deadline. The accepted and presented papers will be published in the conference proceedings and submitted to IEEE Xplore as well as other Abstracting and Indexing (A&I) databases. Independently of the presentation type, all papers are included in the proceedings.​


Workshop Organiser(s)

Manoj Sharma, BVCOE, AFF-G.G.S.I.P.Univ. Delhi, India


Workshop and Symposium Chairs

Axel SikoraUniversity of Applied Sciences Offenburg, Germany
Farag AzzedinKing Fahd University of Petroleum and Minerals,  Saudi Arabia
Sudip Misra, Indian Institute of Technology, Kharagpur, India


Technical Program Committee

Abbas Sheibanyrad, CNRS, France
Ali Beydoun, IUL, Lebanon
Athanasios Kakarountas, Technological Educational Institute of Ionian Islands, Greece
Cristinel Ababei, Marquette University, USA
Deva Nand, Delhi Technological University, Delhi, India
Frank Löffler, Louisiana State University, USA
Hari Chauhan, Northeastern University, USA
Hazem Abbas, Ain Shams University, Egypt
IHsin Chung, IBM T.J Watson Research Center, USA
Jay Merja, Gujarat Technological University, India
John Ronczka, Now Affiliated with Australian Society of Rheology, Australia
Lakshmi Devasena C, IBS, Hyderabad, IFHE University, India
Leonel Sousa, INESC-ID / IST, Technical University of Lisbon, Portugal
Maneesha Gupta, Netaji Subhas Institute of Technolgy, India
Manjunath Gorentla Venkata, Oak Ridge National Laboratory, USA
Mridula Sharma, University of Kassel, Germany
Muhammad Islam, American International University-Bangladesh, Bangladesh
Neeta Pandey, Delhi College of Engineering, India
Rizalafande Che Ismail, Universiti Malaysia Perlis, Malaysia
Rolf Clauberg, IBM Research, Switzerland
Sanjukta Bhowmick, University of Nebraska-Omaha, USA
Satish Tiwari, Netaji Subhas Institute of Technology, India
Sheung-Hung Poon, National Tsing Hua University, Taiwan R.O.C., Taiwan
Soumya Kanti Datta, EURECOM, France
Sujit Mandal, National Institute of Technology, Durgapur, India
Umair Rafique, Mohammad Ali Jinnah University, Pakistan
Vigyan Jain, STMicroelectronics, India
Vitus Leung, Sandia National Labs, USA
Yao Zheng, Zhejiang University, P.R. China
Yi Gu, Middle Tennessee State University, USA


Accepted Papers

Design of Enhanced Arithmetic Logical Unit for Hardware Genetic Processor (Regular paper)
Haramardeep Singh

Capacitor Less Dram Cell Design for High Performance Embedded System (Regular paper)
Prateek Asthana and Sangeeta Mangesh

Low Power Multiplier Using Dynamic Voltage And Frequency Scaling (DVFS) (Regular paper)
Deepak Garg and Rajender Sharma

Logical effort based Power-Delay-Product Optimization (Regular paper)
Sachin Maheshwari, Jimit Patel, Sumit K. Nirmalkar and Anu Gupta

Analysis of Multi–bit Flip Flop Low Power Methodology to Reduce Area and Power in Physical Synthesis and Clock Tree Synthesis in 90nm CMOS Technology (Regular paper)
Saurabh Gautam

Key Dates

 Paper Submission Ends June 13, 2014
 Acceptance Notification July 20, 2014
 Final Paper Deadline August 20, 2014
 Author Registration Closes August 22, 2014
 Conference 24 – 27 September 2014

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